1. Technical Field
Embodiments of the present invention generally relate to the field of integrated circuit package substrates and more particularly, but not exclusively, to fabrication processing that provides microbump interconnects.
2. Background Art
Integrated circuits are typically formed on a semiconductor wafer made of materials such as silicon. The semiconductor wafer is then processed to form various electronic devices. The wafers is usually diced into semiconductor chips (a chip is also known as a die), which may then be attached to a substrate. The substrate is typically designed to couple the die, directly or indirectly, to a printed circuit board, socket, or other connection. The substrate may also perform one or more other functions such as protecting, isolating, insulating, and/or thermally controlling the die.
The substrate (for example, an interposer) has traditionally been formed from a core made up of a laminated multilayer structure. Typically, microbumps and other such interconnect structures are variously formed in or on the structure to facilitate electrical coupling of a die to one or more other devices. Coreless substrates have been developed to decrease the thickness of the substrate. In a coreless substrate, a removable core layer is typically provided, conductive and dielectric layers built up on the removable core, and then the core is removed. The coreless substrate typically includes a plurality of vias formed therein interlayer electrical connections.
As successive generations of fabrication technologies continue to scale in size, metallurgical properties of various materials have an increasingly significant impact on the formation and operation of interconnect structures. Accordingly, there is an increasing demand for incremental improvements in the fabrication of structures to interconnect microelectronic circuit devices.